VERILOG_SOURCES += $(SPINALROOT)/Axi4SharedSdramCtrlTester.v mt48lc16m16a2.v Axi4SharedSdramCtrlTester_tb.v
TOPLEVEL=Axi4SharedSdramCtrlTester_tb
MODULE=Axi4SharedSdramCtrlTester

include ../common/Makefile.sim